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preliminary rev. 0.3 2/08 copyright ? 2008 by silicon laboratories si5323 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5323 p in -p rogrammable p recision c lock m ultiplier /j itter a ttenuator description the si5323 is a jitter-atte nuating precision clock multiplier for high-speed communication systems, including sonet oc-48/oc-1 92, ethernet, and fibre channel. the si5323 accepts dual clock inputs ranging from 8 khz to 707 mhz and generates two equal frequency-multiplied clock outputs ranging from 8 khz to 1050 mhz. the input clock frequency and clock multiplication ratio are selectable from a table of popular sonet, ethernet, and fibre channel rates. the si5323 is based on silicon laborat ories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operating from a single 1.8, 2.5, or 3.3 v supply, the si5323 is ideal for providing clock multiplication and jitter attenu ation in high performance timing applications. applications ? sonet/sdh oc-48/stm-16 and oc-192/stm-64 line cards ? gbe/10gbe, 1/2/4/8/10gfc line cards ? itu g.709 line cards ? optical modules ? test and measurement ? synchronous ethernet features ? selectable output frequencies ranging from 8 khz to 1050 mhz ? ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 khz?80 mhz) ? integrated loop filter with selectable loop bandwidth (60hz to 8.4khz) ? meets oc-192 gr-253-core jitter specifications ? dual clock inputs w/manual or automatically controlled hitless switching ? dual clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) ? support for itu g.709 fec ratios (255/238, 255/237, 255/236) ? lol, los alarm outputs ? pin-controlled output phase adjust ? pin-programmable settings ? on-chip voltage regulator for 1.8 5%, 2.5 or 3.3 v 10% operation ? small size: 6 x 6 mm 36-lead qfn ? pb-free, rohs compliant p reliminary d ata s heet dspll ? loss of signal clock select bandwidth select frequency select disable/bypass xtal or refclock signal format ckout2 ckin1 ckout1 ckin2 control manual/auto switch / skew control signal detect vdd (1.8, 2.5, or 3.3 v) gnd loss of lock rate select
si5323 2 preliminary rev. 0.3 table 1. performance specifications (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current i dd f out = 622.08 mhz both ckouts enabled lvpecl format output 251 279 ma ckout2 disabled ? 217 243 ma f out = 19.44 mhz both ckouts enabled cmos format output ? 204 234 ma ckout2 disabled ? 194 220 ma tristate/sleep mode 165 tbd ma input clock frequency (ckin1, ckin2) ck f input frequency and clock multiplication ratio pin-select- able from table of values using frqsel and frqtbl settings. consult silicon lab- oratories configuration soft- ware dspll sim or any-rate precision clock family reference manual at www.silabs.com/timing (click on documentation) for table selections. 0.008 ? 707.35 mhz output clock frequency (ckout1, ckout2) ck of 0.008 ? 1049.76 mhz 3-level input pins input mid current i imm see note 2. ?2 ? 2 a input clocks (ckin1, ckin2) differential voltage swing ck ndpp 0.25 ? 1.9 vpp common mode voltage ck nvcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ck ntrf 20?80% ? ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns output clocks (ckout1, ckout2) common mode v ocm lvpecl 100 load line-to-line v dd ?1.42 ? v dd ?1.25 v differential output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v rise/fall time cko trf 20?80% ? 230 350 ps notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5323 preliminary rev. 0.3 3 duty cycle uncertainty cko dc lvpecl differential 100 line-to-line measured at 50% point ?40 ? 40 ps pll performance jitter generation j gen f in = f out = 622.08 mhz, lvpecl output format 50 khz?80 mhz ?0.3tbdps rms 12 khz?20 mhz ? 0.3 tbd ps rms jitter transfer j pk ? 0.05 0.1 db external reference jitter transfer j pkextn ?tbdtbddb phase noise cko pn f in = f out = 622.08 mhz 100 hz offset ? tbd tbd dbc/hz 1 khz offset ? tbd tbd dbc/hz 10 khz offset ? tbd tbd dbc/hz 100 khz offset ? tbd tbd dbc/hz 1 mhz offset ? tbd tbd dbc/hz subharmonic noise sp subh phase noise @ 100 khz off- set ? tbd tbd dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? tbd tbd dbc package thermal resistance junction to ambient ja still air ? 38 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.6 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2kv esd mm tolerance; all pins except ckin+/ckin? 200 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 700 v esd mm tolerance; ckin+/ckin? 150 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5323 4 preliminary rev. 0.3 figure 1. typical phase noise plot jitter band jitter, rms brick wall, 100 hz to 100 mhz 1,279 fs sonet_oc48, 12 khz to 20 mhz 315 fs sonet_oc192_a, 20 khz to 80 mhz 335 fs sonet_oc192_b, 4 mhz to 80 mhz 194 fs sonet_oc192_c, 50 khz to 80 mhz 318 fs brick wall, 800 hz to 80 mhz 343 fs 155.52 mhz in, 622.08 mhz out -160 -140 -120 -100 -80 -60 -40 -20 0 100 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz )
si5323 preliminary rev. 0.3 5 figure 2. si5323 typical application circuit si5323 cksel 3 los1 los2 frqsel[3:0] 2 lol bwsel[1:0] 2 sfout[1:0] 2 dbl2_by 2 rst ckout1+ ckout1? input clock select frequency select bandwidth select signal format select clock output 2 disable/ bypass mode control reset ckin_1 loss of signal ckin_2 loss of signal pll loss of lock indicator inc dec skew increment skew decrement frqtbl 2 frequency table select ckout2+ ckout2? autosel 2 manual/automatic clock selection (l) 2. denotes tri-level input pins with states designated as l (ground), m (v dd /2), and h (v dd ). ckin1+ ckin1? input clock sources 1 ckin2+ ckin2? notes: 3. assumes manual input clock selection. rate 2 xa xb crystal crystal/ref clk rate option 1: 1. assumes differential lvpecl termination (3.3 v) on clock inputs. vdd gnd ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 130 130 82 82 v dd = 3.3 v 130 130 82 82 v dd = 3.3 v clock outputs 100 0.1 f 0.1 f + ? 100 0.1 f 0.1 f + ? xa xb ext. refclk+ option 2: 0.1 f ext. refclk? 0.1 f v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k
si5323 6 preliminary rev. 0.3 1. functional description the si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including sonet oc-48/oc-192, ethernet, and fibre channel. the si5323 accepts dual clock inputs ranging from 8 khz to 707 mhz and generates two frequency- multiplied clock outputs ranging from 8 khz to 1050 mhz. the two input clocks are at the same frequency and the two output clocks are at the same frequency. the input clock frequency and clock multiplication ratio are selectable from a table of popular sonet, ethernet, and fibre channel rates. in addition to providing clock multiplic ation in sonet and datacom applications, the si5323 supports sonet-to-datacom frequency translations. silicon laboratories offers a pc- based software utility, dspll sim , that can be used to look up valid si5323 frequency translations. this utility can be downloaded from http://www.silabs.com/timing (click on documentation). the si5323 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5323 pll loop bandwidth is selectable via the bwsel[1:0] pins and supports a range from 60 hz to 8.4 khz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. the si5323 supports hitless switching between the two input clocks in compliance with gr-253-core and gr- 1244-core that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (<200 ps typ). manual and automatic revertive and non-revertive input clock switching options are available via the autosel input pin. the si5323 monitors both input clocks for loss-of-signal and provides a los alarm when it detects missing pulses on either input clock. the device monitors the lock status of the pll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. the si5323 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected inpu t reference is lost. during digital hold, the dspll generates an output frequency based on a historical average that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. the si5323 has two differential clock outputs. the electrical format of the clock outputs is programmable to support lvpecl, lvds, cml, or cmos loads. if not required, the second clock output can be powered down to minimize power consumption. the phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. for system-level debugging, a bypass mode is available which drives the outp ut clock directly from the input clock, bypassing the internal dspll. the device is powered by a single 1.8, 2.5, or 3.3 v supply. 1.1. external reference an external, 38.88 mhz clock or a low-cost 114.285 mhz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the dspll. this external reference is required for the device to perform jitter attenuation. silic on laboratories recommends using a high-quality crystal. specific recommendations may be found in the family reference manual. an external clock from a high quality ocxo or tcxo can also be used as a reference for the device. in digital hold, the dspl l remains locked to this external reference. any changes in the frequency of this reference when the dspll is in digital hold will be tracked by the output of th e device. note that crystals can have temperature sensitivities. 1.2. further documentation consult the silicon laborato ries any-rate precision clock family reference ma nual (frm) for detailed information about the si5323. additional design support is available from silicon laboratories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing (click on documentation).
si5323 preliminary rev. 0.3 7 2. pin descriptions: si5323 pin assignments are preliminary and subject to change. table 3. si5323 pin descriptions pin # pin name i/o signal level description 1rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all in ternal logic to a known state. clock out- puts are tristated during reset. after rising edge of rst sig- nal, the si5323 will perform an internal self-ca libration when a valid input signal is present. this pin has a weak pull-up. 2 frqtbl i 3-level frequency table select. selects sonet/sdh, datacom, or sonet/sdh to datacom frequency table. l=sonet/sdh m = datacom h = sonet/sdh to datacom this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 3c1bolvcmos ckin1 loss of signal. active high loss-of-signal indicator for ckin1. once trig- gered, the alarm will remain ac tive until ckin1 is validated. 0 = ckin1 present 1 = los on ckin1 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 frqtbl autosel rst c2b c1b gnd vdd xa vdd rate0 ckin2+ ckin2? dbl2_by rate1 ckin1+ ckin1? cs_ca bwsel0 bwsel1 frqsel1 frqsel2 frqsel3 ckout1? sfout1 gnd vdd sfout0 ckout2? ckout2+ nc gnd pad frqsel0 inc 9 18 19 28 xb lol dec ckout1+
si5323 8 preliminary rev. 0.3 4c2bolvcmos ckin2 loss of signal. active high loss-of-signal indicator for ckin2. once trig- gered, the alarm will remain ac tive until ckin2 is validated. 0 = ckin2 present 1 = los on ckin2 5, 10, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be as sociated with the following v dd pins: 5 0.1 f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as close to device as is prac- tical. 7 6 xb xa ianalog external crystal or reference clock. external crystal should be con nected to these pins to use internal oscillator based refer ence. refer to family refer- ence manual for interfacing to an external reference. exter- nal reference must be from a high-quality clock source (tcxo, ocxo). frequency of crystal or external clock is set by the rate pins. 8, 31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. 9 autosel i 3-level manual/automatic clock selection. three level input that selects the method of input clock selec- tion to be used. l = manual m = automatic non-revertive h = automatic revertive this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 11 15 rate0 rate1 i 3-level external crystal or reference clock rate. three level inputs that select the type and rate of external crystal or reference clock to be applied to the xa/xb port. refer to the family reference manual for settings. these pins have both a weak pull-up and a weak pull-down and default to m. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 12 13 ckin2+ ckin2? i clock input 2. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from a table of values. the same frequency must be applied to ckin1 and ckin2. table 3. si5323 pin descriptions (continued) pin # pin name i/o signal level description
si5323 preliminary rev. 0.3 9 14 dbl2_by i 3-level output 2 disable/bypass mode control. controls enable of ckout2 divider/output buffer path and pll bypass mode. l = ckout2 enabled m = ckout2 disabled h = bypass mode with ckout2 enabled this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from a table of values. the same frequency must be applied to ckin1 and ckin2. 18 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indica- tor. 0 = pll locked 1 = pll unlocked 19 dec i lvcmos skew decrement. a pulse on this pin decreases the input to output device skew by 1/f osc (approximately 200 ps). there is no limit on the range of skew adjustment by this method. if both inc and dec are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output cloc k during an input clock transi- tion. detailed operations and timing characteristics for this pin may be found in the any-ra te precision clock family reference manual. this pin has a weak pull-down. 20 inc i lvcmos skew increment. a pulse on this pin increases th e input to output device skew by 1/f osc (approximately 200 ps). there is no limit on the range of skew adjustment by this method. if both inc and dec are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output cloc k during an input clock transi- tion. detailed operations and timing characteristics for this pin may be found in the any-ra te precision clock family reference manual. note: if ni_hs = 4, increment is not available. this pin has a weak pull-down. table 3. si5323 pin descriptions (continued) pin # pin name i/o signal level description
si5323 10 preliminary rev. 0.3 21 cs_ca i/o lvcmos input clock select/active clock indicator. input : if manual clock sele ction mode is chosen (autosel = l), this pin functions as the manual input clock selector. this inpu t is internally deglitched to prevent inadvertent clock switching during changes in the cs input state. 0 = select ckin1 1 = select ckin2 if configured as input, must be set high or low. output : if automatic clock selection mode is chosen (autosel = m or h), this pin indicates which of the two input clocks is currently the active clock. if alarms exist on both ckin1 and ckin2, indicating that the digital hold stat e has been entered, ca will indicate the last active clock that was used before entering the hold state. 0 = ckin1 active input clock 1 = ckin2 active input clock 23 22 bwsel1 bwsel0 i 3-level bandwidth select. three level inputs that select the dspll closed loop band- width. detailed operations and timing characteristics for these pins may be found in the any-rate precision clock family reference manual. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 27 26 25 24 frqsel3 frqsel2 frqsel1 frqsel0 i 3-level multiplier select. three level inputs that select the input clock and clock multi- plication ratio, depending on the frqtbl setting. consult the any-rate precision clock family reference manual or dspllsim configuration software for settings, both available for download at www.silabs.com/timing (click on documenta- tion). these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 29 28 ckout1? ckout1+ omulti clock output 1. differential output clock with a frequency selected from a table of values. output signal format is selected by sfout pins. output is differential for lvpecl, lvds, and cml com- patible modes. for cmos format, both output pins drive identical single-ended clock outputs. table 3. si5323 pin descriptions (continued) pin # pin name i/o signal level description
si5323 preliminary rev. 0.3 11 33 30 sfout0 sfout1 i 3-level signal format select. three level inputs that select the output signal format (com- mon mode voltage and differential swing) for both ckout1 and ckout2. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 34 35 ckout2? ckout2+ omulti clock output 2. differential output clock with a frequency selected from a table of values. output signal format is selected by sfout pins. output is differential for lvpecl, lvds, and cml com- patible modes. for cmos format, both output pins drive identical single-ended clock outputs. 36 nc ? ? no connect. these pins must be left unc onnected for normal operation. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5323 pin descriptions (continued) pin # pin name i/o signal level description sfout[1:0] signal format hh reserved hm lvds hl cml mh lvpecl mm reserved ml lvds?low swing lh cmos lm disable ll reserved
si5323 12 preliminary rev. 0.3 3. ordering guide ordering part number package roh s6, pb-free temperature range si5323-c-gm 36-lead 6 x 6 mm qfn yes ?40 to 85 c
si5323 preliminary rev. 0.3 13 4. package outline: 36-pin qfn figure 3 illustrates the package details for the si5323. table 4 lis ts the values for the di mensions shown in the illustration. figure 3. 36-pin quad flat no-lead (qfn) table 4. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specif ication for small body components.
si5323 14 preliminary rev. 0.3 5. recommended pcb layout figure 4. pcb land pattern diagram
si5323 preliminary rev. 0.3 15 table 5. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5323 16 preliminary rev. 0.3 d ocument c hange l ist revision 0.1 to revision 0.2 ? changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 3. ? added figure 1, ?typical phase noise plot,? on page 4. ? updated figure 2, ?si5323 typical application circuit,? on page 5 to show external reference interface. ? added rate0 and expanded the rate[1:0] description in 2. "pin descriptions: si5323?. ? updated 3. "ordering guide" on page 12. ? added 5. "recommended pcb layout?. revision 0.2 to revision 0.3 ? changed 1.8 v operating range to 5%. ? updated table 1 on page 2. ? updated table 2 on page 3. ? added table under figure 1 on page 4. ? updated 1. "functional description" on page 6. ? clarified 2. "pin descriptions: si5323" on page 7 including pull-up/pull-down. ? updated sfout values.
si5323 preliminary rev. 0.3 17 n otes :
si5323 18 preliminary rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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